1. Field of the Invention
The present invention generally relates to the fabrication of field effect transistors (FETs) having lightly-doped drain (LDD) regions; more particularly, to the formation and removal of LDD spacers.
2. Description of the Related Art
Lightly-doped drain (LDD) regions have commonly been used in reducing the length of the channel region in an FET, thereby reducing the size of transistor. The reduction in the length of the channel region is made possible by LDD regions which separate the source and drain regions from the channel region, and thus increase the channel breakdown voltage and reduce electron impact ionization (hot electron effects) by reducing the electric field at the source and drain pinch-off regions.
An FET having LDD regions is typically fabricated in an active region of a substrate. The active region is bounded by field oxide (FOX) regions which electrically isolate the FET from other devices formed in the same substrate. Conventional processing techniques are utilized to implant regions at both ends of a gate with a light dose of an N/P-type dopant using the gate as a mask. Two N.sup.- /P.sup.- regions formed by the implant define a channel underlying the gate. (Either N-type or P-type dopants may be utilized, and portion of the following discussion which refer only to P-type dopants are for convenience only. In some cases, where either N-or P-type dopants may be used, the dopant type will be noted as N/P. A spacer material layer is formed over the entire structure and etched so that spacers remain at the ends of the gate. These spacers overlie portions of the N.sup.- /P.sup.- regions adjacent to the gate structures. Thereafter, a second implant is performed with a heavier dose of an N/P-type dopant to form N.sup.+ /P.sup.+ source and drain regions. During the second implant the spacers mask the underlying N.sup.- /P.sup.- regions. The N.sup.- /P.sup.- regions which do not receive the second implant become the LDD regions. Thus, the width of the spacers defines the width of the implanted LDD regions.
The conventional manner of forming spacers is to perform a blanket etch of the spacer material layer. Because there are non-uniformities in the thickness of the spacer material layer, and because of non-uniformities of the etching rate over the entire wafer area, there are areas of the wafer where over-etching occurs and other areas where there is an incomplete removal of the spacer material layer. Conventionally, the spacer material layer is an oxide (usually a CVD oxide), and it is critical that the oxide layer be completely removed from the top of the gate and from the portions of the active region overlying the source and drain regions. However, when the strength of the etchant and the etching time are adjusted to assure complete removal of the oxide from the gate and S/D regions, the etchant often removes material from the field oxide regions. Typically, 1,000-2,000.ANG. of the field oxide is removed. Removal of the field oxide, referred to as oxide loss, reduces the threshold breakdown voltage between the metalization layers and the substrate. Further, oxide loss results in a degradation of device isolation.
Further, it is desirable to select an etching time which provides the proper width of the spacers, rather than basing the etching time on complete removal of the spacer material layer. While the channel breakdown voltage of an LDD FET and its ability to resist hot electron effects can be increased by increasing the width of the LDD regions, the LDD regions can increase the series resistance of the transistor channel and degrade the current drive capability of the FET. Consequently, it is important to control the fabrication process so that an optimum LDD width is achieved.
One proposed method of reducing oxide loss is to form the spacer material layer from a thin layer of thermal oxide, e.g., SiO.sub.2, (for protecting the substrate) and a thicker layer of polysilicon overlying the thermal oxide. The polysilicon layer is then etched with an etchant which has a much higher etch rate for polysilicon than for the silicon oxide to form the spacers at the ends of the gate. Because the etchant selectively etches polysilicon, the oxide layer protects the source and drain regions from etching.
If the spacers are formed of an oxide, the spacers may be left in the device--since the oxide is an insulator, the oxide does not disturb the electrical characteristics of the device. Polysilicon is conductive and must be removed before the device is completed. It is, however, very difficult to remove the polysilicon spacers after the N.sup.+ /P.sup.+ implant since the implant process forms a skin on the surface of the polysilicon; in the case of the P-type dopant boron, the skin is a boron skin. The device must then be exposed to the etchant for a period which is long enough for the etchant to penetrate the skin on the polysilicon spacers, usually a period which allows the etchant to penetrate the oxide layer protecting the source and drain regions and to remove a significant amount of oxide from the FOX regions. After penetrating the protective oxide layer, the etchant will attack the substrate in the source and drain regions, thereby destroying the device being fabricated.